`define     IF2ID_BUS_WD        177 // StageIF to StageID Bus Width
`define     ID2EX_BUS_WD        563 // StageID to StageEX Bus Width
`define     EX2MA_BUS_WD        449 // StageEX to StageMA Bus Width
`define     MA2WB_BUS_WD        344 // StageMA to StageWB Bus Width

`define     BJ_BUS_WD           66  // BranchJumpUnit to StageIF Bus Width

`define     EX_RF_HZD_BUS_WD    71  // StageEX to StageID Forward & Block Bus Width
`define     MA_RF_HZD_BUS_WD    71  // StageMA to StageID Forward & Block Bus Width
`define     WB_RF_HZD_BUS_WD    71  // StageWB to StageID Forward & Block Bus Width

`define     ID2RF_BUS_WD        10  // StageID to Regfile Bus Width
`define     RF2ID_BUS_WD        128 // Regfile to StageID Bus Width
`define     WB2RF_BUS_WD        70  // StageEX to Regfile Bus Width
`define     WB2CSR_BUS_WD       239 // StageWB to CSR Bus Width

`define     EX_CSR_BLK_BUS_WD   13 
`define     MA_CSR_BLK_BUS_WD   13
`define     WB_CSR_BLK_BUS_WD   13

`define CSR_ADDR_MSTATUS        12'h300
`define CSR_ADDR_MIE            12'h304
`define CSR_ADDR_MTVEC          12'h305
`define CSR_ADDR_MEPC           12'h341
`define CSR_ADDR_MCAUSE         12'h342
`define CSR_ADDR_MIP            12'h344
